Field of the Invention
The invention relates to a technology for managing commands of a memory.
Description of the Related Art
Memories are an essential element in many electronic products. Low power double data rate 2/3 (LPDDR2/3) memories, featuring low power consumption and high reliability, are extensively applied in portable consumer electronic products.
An LPDDR2/3 memory has ten command/address pins (CA0 to CA9) for receiving commands including reading, writing and pre-charging issued from an external control circuit and addresses associated with these commands. To increase an operation speed, an LPDDR2/3 memory is designed to access signals from the pins CA0 to CA9 at both a rising edge and a falling edge of a clock signal CK_t. FIG. 1(A) shows a partial mapping table of LPDDR specifications. In the table, the symbol H represents a high level voltage, L represents a low level voltage, and X represents a negligible voltage status. In addition to the command/address pins CA0 to CA9, an LPDDR2/3 memory further includes two pins for transmitting control signals—a clock enable pin CKE and a chip select pin CS_N. Taking an activate (Act) command for example, assuming that the signal statuses of the clock enable pin CKE at a time pint CK_t(n−1) and a time point CK_t(n) are both H, and the memory respectively accesses L, L and H from the chip select pin CS_N and the command/address pin CA0 and CA1 at a rising edge of the clock signal CK_t, the memory determines that an external control circuit issues an Act command. Meanwhile, the information that the memory accesses from the command/address pins CA2 to CA9 is a part of designated addresses of a memory area to be activated. When a falling edge of the clock signal CK_t later appears, the memory may access the other part of address information from the command/address pins CA0 to CA9.
For a no-operation (NOP) command, assuming that the signal statuses of the clock enable pin CKE at the time point CK_t(n−1) and CK_t(n) are both H, and the memory accesses H from the chip select pin CS_N at a rising edge of the clock signal CK_t, the memory may determine that the external control circuit issues a NOP command. In such situation, the memory may omit the signals accessed at the same time from the command/address pins CA0 to CA9, and may also omit the signals on the command/address pins CA0 to CA9 when a falling edge of the clock signal CK_t later appears.
FIG. 1(B) shows an example of a possible timing diagram of pins of an LPDDR2/3 memory in actual operations. A clock signal CK_t is a periodical square wave signal having a duty cycle of substantially equal to 50%, and it is assumed that the cycle length is T. In this example, an external control circuit sequentially issues a no-operation (NOP) command, an Act command, a NOP command, a read (RD) command, and a longer NOP command via the command/address pins CA0 to CA9. As seen from FIG. 1(B), to allow the LPDDR2/3 memory to correctly access the first part of the Act command from the command/address pins CA0 to CA9 at a rising edge of the clock signal CK_t at a time point t3, the external control circuit changes voltage statuses of the command/address pins CA0 to CA9 at an intermediate time point between the time points t2 and t3, such that the signals on the command/address pins CA0 to CA9 complete the transition before the time point t3. Between time points t3 and t4, the external control circuit causes the signals on the command/address pins CA0 to CA9 to complete the transition, so that the LPDDR2/3 memory is allowed to correctly access the second part of the Act command from the command/address pins CA0 to CA9 at a falling edge of the clock signal CK_t at the time point t4.
Similarly, to allow the LPDDR2/3 memory to correctly access the first part of the RD command from the command/address pins CA0 to CA9 at a rising edge of the clock signal CK_t at the time point t7, the external control circuit changes the voltage statuses of the command/address pins CA0 to CA9 at an intermediate point between the time points t6 and t7 to cause the signals on the command/address pins CA0 to CA9 to complete the transition before the time point t7. Between time points t7 and t8, the external control circuit causes the signals on the command/address pins CA0 to CA9 to complete the transition, so that the LPDDR2/3 memory is allowed to correctly access the second part of the RD command from the command/address pins CA0 to CA9 at a falling edge of the clock signal CK_t at the time point t8.
The above method suffers from one drawback. That is, each time when a new command appears, multiple signals among the signals transmitted on the command/address pins CA0 to CA9 may transition at a same time point. For example, there are nine signals concurrently in transition at the intermediate time point between the time points t2 and t3, and there are ten signals concurrently in transition at the intermediate time point between the time points t6 and t7. These signals concurrently in transition may interfere one another and result in poor signal quality. Further, these signals concurrently in transition may cause a quite large instantaneous current/voltage fluctuation, or cause a high power demand during the instant of the transition.
On the other hand, as the LPDDR2/3 memory accesses data at both a rising edge and a falling edge of the clock signal CK_t, the aperture of an eye diagram of accessed results can be limited, which may lead to possible misjudgment on the accessed results. Taking the command/address pin CA2 in FIG. 1(B) for example, the voltage changes from low to high between the time points t2 and t3, and changes from high to low between the time points t3 and t4. If the transition time of this signal is slightly delayed or brought forward due to various non-ideal factors or the clock signals at transmitter and receiver ends are not ideally synchronized, the LPDDR2/3 memory may access an incorrect voltage status, leading to a misjudgment on the command issued from the external control circuit.